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LTC1599 16-Bit Byte Wide, Low Glitch Multiplying DAC with 4-Quadrant Resistors
FEATURES
s s s
DESCRIPTIO
s s
s s s s s
True 16-Bit Performance over Industrial Temperature Range DNL and INL: 1LSB Max On-Chip 4-Quadrant Resistors Allow Precise 0V to 10V, 0V to - 10V or 10V Outputs 2s Settling Time to 0.0015% (with LT(R)1468) Asynchronous Clear Pin Resets to Zero Scale or Midscale Glitch Impulse: 1.5nV-s 24-Lead SSOP Package Low Power Consumption: 10W Typ Power-On Reset to Zero Scale or Midscale 2-Byte Parallel Digital Interface
APPLICATIO S
s s s s
Process Control and Industrial Automation Direct Digital Waveform Generation Software-Controlled Gain Adjustment Automatic Test Equipment
The LTC (R)1599 is a 2-byte parallel input 16-bit multiplying current output DAC that operates from a single 5V supply. INL and DNL are accurate to 1LSB over the industrial temperature range in both 2- and 4-quadrant multiplying modes. True 16-bit 4-quadrant multiplication is achieved with on-chip 4-quadrant multiplication resistors. The LTC1599 is available in 24-pin PDIP and SSOP packages and is specified over the commercial and industrial temperature ranges. The device includes an internal deglitcher circuit that reduces the glitch impulse to 1.5nV-s (typ). The asynchronous CLR pin resets the LTC1599 to zero scale when the CLVL pin is at a logic low and to midscale when the CLVL pin is at a logic high. For a full 16-bit wide parallel interface current output DAC, refer to the LTC1597 data sheet. For serial interface 16-bit current output DACs, refer to the LTC1595/LTC1596 data sheet.
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATIO
VREF -VREF 3
A 16-Bit, 4-Quadrant Multiplying DAC with a Minimum of External Components
5V LT1468 6 0.1F
4 R1 8 DATA INPUTS 14 TO 18, 21 TO 23 MLBYTE 13 MLBYTE R1
3 RCOM R2
INTEGRAL NONLINEARITY (LSB)
LTC1599
16-BIT DAC IOUT2S DGND 19
9
WR LD CLR WR LD CLR CLVL 12 11 24
CLVL 10
+
IOUT2F
8
3
-
-
2
15pF
2
1
20 5 VCC ROFS ROFS RFB
6 RFB 15pF IOUT1 7 2
R2 REF
VREF LT1468 6 VOUT = -VREF
1599 TA01
U
Integral Nonlinearity
1.0 0.8 0.6 0.4 0.2 0 - 0.2 - 0.4 - 0.6 - 0.8 -1.0 0 49152 32768 16384 DIGITAL INPUT CODE 65535
1599 G08
U
U
+
1
LTC1599
ABSOLUTE MAXIMUM RATINGS
(Note 1)
PACKAGE/ORDER INFORMATION
TOP VIEW REF R2 RCOM R1 ROFS RFB IOUT1 IOUT2F IOUT2S 1 2 3 4 5 6 7 8 9 24 CLR 23 D0 22 D1 21 D2 20 VCC 19 DGND 18 D3 17 D4 16 D5 15 D6 14 D7 13 MLBYTE N PACKAGE 24-LEAD PDIP
VCC to DGND .............................................. - 0.3V to 7V REF, ROFS, RFB, R1, R2 to DGND .......................... 25V RCOM ........................................................ - 0.3V to 12V Digital Inputs to DGND ............... - 0.3V to (VCC + 0.3V) IOUT1, IOUT2F, IOUT2S to DGND .... - 0.3V to( VCC + 0.3V) Maximum Junction Temperature .......................... 125C Operating Temperature Range LTC1599C ............................................... 0C to 70C LTC1599I ............................................ - 40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
ORDER PART NUMBER LTC1599ACG LTC1599BCG LTC1599AIG LTC1599BIG LTC1599ACN LTC1599BCN LTC1599AIN LTC1599BIN
CLVL 10 LD 11 WR 12 G PACKAGE 24-LEAD PLASTIC SSOP
TJMAX = 125C, JA = 95C/ W (G) TJMAX = 125C, JA = 58C/ W (N)
Consult factory for Military grade parts.
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 5V 10%, VREF = 10V, IOUT1 = IOUT2F = IOUT2S = DGND = 0V, TA = TMIN to TMAX unless otherwise noted.
SYMBOL PARAMETER Accuracy Resolution Monotonicity INL DNL GE Integral Nonlinearity Differential Nonlinearity Gain Error TA = 25C (Note 2) TMIN to TMAX TA = 25C TMIN to TMAX Unipolar Mode TA = 25C (Note 3) TMIN to TMAX Bipolar Mode TA = 25C (Note 3) TMIN to TMAX Gain Temperature Coefficient Bipolar Zero Error ILKG PSRR OUT1 Leakage Current Power Supply Rejection Gain/Temperature (Note 4) TA = 25C TMIN to TMAX TA = 25C (Note 5) TMIN to TMAX VCC = 5V 10%
q q q q
ELECTRICAL CHARACTERISTICS
CONDITIONS
MIN 16 16
LTC1599B TYP
MAX
MIN 16 16
LTC1599A TYP
MAX
UNITS Bits Bits
2 2 1 1 16 24 16 24 1 3 10 16 5 15 1 2
0.25 0.35 0.2 0.2 2 3 2 3 1
1 1 1 1 16 16 16 16 3 5 8 5 15
q
q q q q q
ppm/C LSB LSB nA nA LSB/V
1
2
2
U
W
U
U
WW
W
LSB LSB LSB LSB LSB LSB LSB LSB
LTC1599
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 5V 10%, VREF = 10V, IOUT1 = IOUT2F = IOUT2S = DGND = 0V, TA = TMIN to TMAX unless otherwise noted.
SYMBOL RREF R1, R2 ROFS, RFB PARAMETER DAC Input Resistance (Unipolar) R1, R2 Resistance (Bipolar) Feedback and Offset Resistances Output Current Settling Time Midscale Glitch Impulse Digital-to-Analog Glitch Impulse Multiplying Feedthrough Error THD Total Harmonic Distortion Output Noise Voltage Density Analog Outputs (Note 4) COUT Output Capacitance (Note 4) DAC Register Loaded to All 1s: COUT1 DAC Register Loaded to All 0s: COUT1
q q
ELECTRICAL CHARACTERISTICS
Reference Input (Note 6)
CONDITIONS
q q q
MIN 4.5 9 9
TYP 6 14 13.5 1 1.5 1 1 108 10 115 70
MAX 10 20 20
UNITS k k k s nV-s nV-s mVP-P dB nV/Hz
(Notes 6, 13) (Note 6) (Notes 7, 8) (Note 12) (Note 9) VREF = 10V, 10kHz Sine Wave (Note 10) (Note 11)
AC Performance (Note 4)
130 80
pF pF V
Digital Inputs VIH VIL IIN CIN tDS tDH tWR tBWS tBWH tLD tCLR tLWD VCC ICC Digital Input High Voltage Digital Input Low Voltage Digital Input Current Digital Input Capacitance Data to WR Setup Time Data to WR Hold Time WR Pulse Width MLBYTE to WR Setup Time MLBYTE to WR Hold Time LD Pulse Width Clear Pulse Width WR to LD Delay Time Supply Voltage Supply Current Digital Inputs = 0V or VCC (Note 4) VIN = 0V
q q q q
2.4 0.8 0.001 1 8 80 0 80 0 0 150 150 0 4.5 5 5.5 10 20 -12 25 -12 -12 55 50
V A pF ns ns ns ns ns ns ns ns V A
Timing Characteristics
q q q q q q q q
Power Supply
q q
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: 1LSB = 0.0015% of full scale = 15.3ppm of full scale. Note 3: Using internal feedback resistor. Note 4: Guaranteed by design, not subject to test. Note 5: I(OUT1) with DAC register loaded to all 0s. Note 6: Typical temperature coefficient is 100ppm/C. Note 7: IOUT1 load = 100 in parallel with 13pF. Note 8: To 0.0015% for a full-scale change, measured from the falling edge of LD.
Note 9: VREF = 0V. DAC register contents changed from all 0s to all 1s or all 1s to all 0s. LD high, WR and MLBYTE pulsed. Note 10: VREF = 6VRMS at 1kHz. DAC register loaded with all 1s. RL = 600. Unipolar mode op amp = LT1468. Note 11: Calculation from en = 4kTRB where: k = Boltzmann constant (J/K), R = resistance (), T = temperature (K), B = bandwidth (Hz). Note 12: Midscale transition code 0111 1111 1111 1111 to 1000 0000 0000 0000. Note 13: R1 and R2 are measured between R1 and RCOM, R2 and RCOM.
3
LTC1599 TYPICAL PERFOR A CE CHARACTERISTICS
Midscale Glitch Impulse
40 30 USING AN LT1468 CFEEDBACK = 30pF VREF = 10V
SIGNAL/(NOISE + DISTORTION) (dB)
OUTPUT VOLTAGE (mV)
20 10 0 -10 -20 - 30 - 40 0 0.2 0.4 0.6 TIME (s) 0.8 1.0
1599 G01
1.5nV-s TYPICAL
Bipolar Multiplying Mode Signal-to-(Noise + Distortion) vs Frequency, Code = All Zeros
- 40
SIGNAL/(NOISE + DISTORTION) (dB)
- 50 - 60 - 70 - 80
SIGNAL/(NOISE + DISTORTION) (dB)
- 60 - 70 - 80
SUPPLY CURRENT (mA)
VCC = 5V USING TWO LT1468s CFEEDBACK = 15pF RL = 600 REFERENCE = 6VRMS
500kHz FILTER - 90 80kHz FILTER 30kHz FILTER 10 100 1k 10k FREQUENCY (Hz) 100k
1599 G04
-100
-110
Logic Threshold vs Supply Voltage
3.0 INTEGRAL NONLINEARITY (LSB) 2.5 LOGIC THRESHOLD (V) 2.0 1.5 1.0 0.5 0
DIFFERENTIAL NONLINEARITY (LSB)
0
1
5 2 3 4 SUPPLY VOLTAGE (V)
4
UW
6 7
1599 G07
Full-Scale Settling Waveform
- 40 - 50 - 60 - 70 - 80
Unipolar Multiplying Mode Signal-to-(Noise + Distortion) vs Frequency
VCC = 5V USING AN LT1468 CFEEDBACK = 30pF RL = 600 REFERENCE = 6VRMS
LD PULSE 5V/DIV GATED SETTLING WAVEFORM 500V/DIV
500kHz FILTER - 90 80kHz FILTER 30kHz FILTER 10 100 1k 10k FREQUENCY (Hz) 100k
1599 G03
500ns/DIV USING LT1468 OP AMP CFEEDBACK = 20pF 0V to 10V STEP
1599 G02
-100
-110
Bipolar Multiplying Mode Signal-to-(Noise + Distortion) vs Frequency, Code = All Ones
- 40 - 50 VCC = 5V USING TWO LT1468s CFEEDBACK = 15pF RL = 600 REFERENCE = 6VRMS
5
Supply Current vs Input Voltage
VCC = 5V ALL DIGITAL INPUTS TIED TOGETHER
4
3
500kHz FILTER - 90 80kHz FILTER 30kHz FILTER
2
1
-100 -110 10 100
1k 10k FREQUENCY (Hz)
100k
1599 G05
0
0
1
3 2 INTPUT VOLTAGE (V)
4
5
1599 G06
Integral Nonlinearity (INL)
1.0 0.8 0.6 0.4 0.2 0 - 0.2 - 0.4 - 0.6 - 0.8 -1.0 0 49152 32768 16384 DIGITAL INPUT CODE 65535
1599 G08
Differential Nonlinearity (DNL)
1.0 0.8 0.6 0.4 0.2 0 - 0.2 - 0.4 - 0.6 - 0.8 -1.0 0 49152 32768 16384 DIGITAL INPUT CODE 65535
1598 G09
LTC1599 TYPICAL PERFOR A CE CHARACTERISTICS
Integral Nonlinearity vs Reference Voltage in Unipolar Mode
1.0 0.8
INTEGRAL NONLINEARITY (LSB)
INTEGRAL NONLINEARITY (LSB)
0.6 0.4 0.2 0 - 0.2 - 0.4 - 0.6 - 0.8 -1.0 -10 - 8 - 6 - 4 - 2 0 2 4 6 REFERENCE VOLTAGE (V) 8 10
0.6 0.4 0.2 0 - 0.2 - 0.4 - 0.6 - 0.8 -1.0 -10 - 8 - 6 - 4 - 2 0 2 4 6 REFERENCE VOLTAGE (V) 8 10
DIFFERENTIAL NONLINEARITY (LSB)
Differential Nonlinearity vs Reference Voltage in Bipolar Mode
1.0 1.0 0.8
INTEGRAL NONLINEARITY (LSB)
DIFFERENTIAL NONLINEARITY (LSB)
0.8 0.6 0.4 0.2 0 - 0.2 - 0.4 - 0.6 - 0.8 -1.0 -10 - 8 - 6 - 4 - 2 0 2 4 6 REFERENCE VOLTAGE (V) 8 10
Integral Nonlinearity vs Suppy Voltage in Bipolar Mode
2.0
DIFFERENTIAL NONLINEARITY (LSB)
INTEGRAL NONLINEARITY (LSB)
1.5 1.0 0.5 0 VREF = 10V VREF = 2.5V -1.0 -1.5 -2.0 2 3 4 5 6 SUPPLY VOLTAGE (V) 7
1599 G15
- 0.5
UW
1599 G10
Integral Nonlinearity vs Reference Voltage in Bipolar Mode
1.0 0.8 1.0 0.8 0.6 0.4 0.2 0 - 0.2 - 0.4 - 0.6 - 0.8
Differential Nonlinearity vs Reference Voltage in Unipolar Mode
-1.0 -10 - 8 - 6 - 4 - 2 0 2 4 6 REFERENCE VOLTAGE (V)
8
10
1599 G11
1599 G12
Integral Nonlinearity vs Suppy Voltage in Unipolar Mode
0.6 0.4 0.2 0 - 0.2 - 0.4 - 0.6 - 0.8 -1.0 2 3 4 5 6 SUPPLY VOLTAGE (V) 7
1599 G14
VREF = 10V VREF = 2.5V VREF = 10V VREF = 2.5V
1599 G13
Differential Nonlinearity vs Suppy Voltage in Unipolar Mode
1.0 0.8 0.6 0.4 0.2 0 - 0.2 - 0.4 - 0.6 - 0.8 -1.0 2 3 4 5 6 SUPPLY VOLTAGE (V) 7
1599 G16
VREF = 10V VREF = 2.5V
VREF = 10V VREF = 2.5V
VREF = 10V VREF = 2.5V
5
LTC1599 TYPICAL PERFOR A CE CHARACTERISTICS
Differential Nonlinearity vs Supply Voltage in Bipolar Mode
1.0
DIFFERENTIAL NONLINEARITY (LSB)
0.8 0.6
ATTENUATION (dB)
0.4 0.2 0 - 0.2 - 0.4 - 0.6 - 0.8 VREF = 2.5V VREF = 2.5V VREF = 10V VREF = 10V
-1.0 2 3 4 5 6 SUPPLY VOLTAGE (V) 7
1599 G17
Bipolar Mulitplying Mode Frequency Response vs Digital Code
0 - 20
ALL BITS ON D15 AND D14 ON D15 AND D13 ON D15 AND D12 ON D15 AND D11 ON D15 AND D10 ON D15 AND D9 ON D15 AND D8 ON D15 AND D7 ON D15 AND D6 ON D15 AND D5 ON D15 AND D4 ON D15 AND D3 ON D15 AND D2 ON
ATTENUATION (dB)
- 40 - 60 - 80
ATTENUATION (dB)
- 100 10 100
*DAC ZERO VOLTAGE OUTPUT LIMITED BY BIPOLAR ZERO ERROR TO - 96dB TYPICAL (-78dB MAX, A GRADE) VREF
+
LT1468 - 12pF 12pF 15pF 3 2 LTC1599 145 6 7 22 VOUT
12pF
6
UW
Unipolar Mulitplying Mode Frequency Response vs Digital Code
0 - 20 - 40 - 60 - 80
ALL BITS ON D15 ON D14 ON D13 ON D12 ON D11 ON D10 ON D9 ON D8 ON D7 ON D6 ON D5 ON D4 ON D3 ON D2 ON D1 ON D0 ON ALL BITS OFF
- 100
- 120 100
1k
10k 100k FREQUENCY (Hz)
1M
10M
1599 G18
VREF 32145 LTC1599 7 22 6
30pF
- LT1468 +
VOUT
Bipolar Mulitplying Mode Frequency Response vs Digital Code
0 - 20
ALL BITS OFF D14 ON D14 AND D13 ON D14 TO D12 ON D14 TO D11 ON D14 TO D10 ON D14 TO D9 ON D14 TO D8 ON D14 TO D7 ON D14 TO D6 ON D14 TO D5 ON D14 TO D4 ON D14 TO D3 ON D14 TO D2 ON D14 TO D1 ON
- 40
- 60
CODES FROM MIDSCALE TO FULL SCALE
- 80
D15 AND D1 ON D15 AND D0 ON D15 ON*
CODES FROM MIDSCALE TO ZERO SCALE
D14 TO D0 ON
- 100
D15 ON*
100k 1k 10k FREQUENCY (Hz)
1M
10M
1599 G19
10
100
1k 10k 100k FREQUENCY (Hz)
1M
10M
1599 G20
*DAC ZERO VOLTAGE OUTPUT LIMITED BY BIPOLAR ZERO ERROR TO - 96dB TYPICAL (-78dB MAX, A GRADE) VREF
+
LT1468 - 12pF 15pF 3 2 LTC1599 145 6 7 22 VOUT
- LT1468 +
- LT1468 +
LTC1599
PIN FUNCTIONS
REF (Pin 1): Reference Input. Typically 10V, accepts up to 25V. In 2-quadrant mode, this pin is the reference input. In 4-quadrant mode, this pin is driven by external inverting reference amplifier. R2 (Pin 2): 4-Quadrant Resistor R2. Typically 10V, accepts up to 25V. In 2-quadrant operation, connect this pin to ground. In 4-quadrant mode tie to the REF pin and to the output of an external amplifier. See Figures 1 and 3. RCOM (Pin 3): Center Tap Point of the Two 4-Quadrant Resistors R1 and R2. Normally tied to the inverting input of an external amplifier in 4-quadrant operation, otherwise connect this pin to ground. See Figures 1 and 3. The absolute maximum voltage range on this pin is - 0.3V to 12V. R1 (Pin 4): 4-Quadrant Resistor R1. Typically 10V, accepts up to 25V. In 2-quadrant operation connect this pin to ground. In 4-quadrant mode tie to ROFS (Pin 5). See Figures 1 and 3. ROFS (Pin 5): Bipolar Offset Resistor. Typically swings 10V, accepts up to 25V. In 2-quadrant operation, tie to RFB. In 4-quadrant operation tie to R1. RFB (Pin 6): Feedback Resistor. Normally tied to the output of the current to voltage converter op amp. Typically swings 10V. Swings VREF. IOUT1 (Pin 7): DAC Current Output. Tie to the inverting input of the current to voltage converter op amp. IOUT2F (Pin 8): Force Complement Current Output. Normally tied to ground. IOUT2S (Pin 9): Sense Complement Current Output. Normally tied to ground. CLVL (Pin 10): Clear Level. CLVL = 0, selects reset to zero code. CLVL = 1, selects reset to midscale code. Normally hardwired to a logic high or a logic low. LD (Pin 11): DAC Digital Input Load Control Input. When LD is taken to a logic low, data is loaded from the input register into the DAC register, updating the DAC output. WR (Pin 12): DAC Digital Write Control Input. When WR is taken to a logic low, data is loaded from the 8 digital input pins into the 16-bit wide input register. The MLBYTE pin determines whether the MSB or LSB byte is loaded. MLBYTE (Pin 13): MSB or LSB Byte Select. When MLBYTE is taken to a logic low and WR is taken to a logic low, data is loaded from the 8 digital input pins into the first 8 bits of the 16-bit wide input register. When MLBYTE is taken to a logic high and WR is taken to a logic low, data is loaded from the 8 digital input pins into the 8 MSB bits of the input register. D7 to D3 (Pins 14 to 18): Digital Input Data Bits. DGND (Pin 19): Digital Ground. Tie to ground. VCC (Pin 20): The Positive Supply Input. 4.5V VCC 5.5V. Requires a bypass capacitor to ground. D2 to D0 (Pins 21 to 23): Digital Input Data Bits. CLR (Pin 24): Digital Clear Control Function for the DAC. When CLR and CLVL are taken to a logic low, the DAC output and all internal registers are set to zero code. When CLR is taken to a logic low and CLVL is taken to a logic high, the DAC output and all internal registers are set to midscale code.
TRUTH TABLE
Table 1
CLR 0 1 1 1 1 1 1 1 CONTROL INPUTS WR MLBYTE X X 0 1 X X X 1 LD X 1 1 REGISTER OPERATION Reset Input and DAC Registers to Zero Scale When CLVL = 0 and Midscale When CLVL = 1 Load the LSB Byte of the Input Register with All 8 Data Bits Load the MSB Byte of the Input Register with All 8 Data Bits Load the DAC Register with the Contents of the Input Register No Register Operation Flow-Through Mode. The DAC Register and the Selected Input Register Are Transparent. The Unselected Input Register Retains Its Previous Data Byte. Note Only One Byte Is Transparent at a Time, the Selected Byte Being Determined By the Logic Value of MLBYTE Prior to WR Being Pulsed Low.
U
U
U
7
LTC1599
BLOCK DIAGRA
REF 1 R 48k 12k RCOM 3 12k R1 4
R2 2
VCC 20 DECODER
LD 11
WR 12 MLBYTE 13
MSB ENABLE BYTE ENABLE LOGIC LSB ENABLE
TI I G DIAGRA
MLBYTE tBWS WR tWR D0 TO D7 tDS LD tLWD CLR tCLR
1599 TD
8
W
W
48k 48k 6 RFB 48k 48k 48k 48k 48k 48k 96k 96k 96k 96k 12k 12k 5 ROFS 7 IOUT1 8 IOUT2F 9 IOUT2S 19 DGND LOAD D15 (MSB) D14 D13 D12 D11 *** DAC REGISTER D0 (LSB) RST POWER-ON RESET LOGIC 24 CLR 10 CLVL EN INPUT REGISTER MSB BYTE EN INPUT REGISTER LSB BYTE RST
1599 BD
14 D7
15 D6
****
18 D3
21 D2
22 D1
23 D0
UW
tBWH
tBWH
tBWS
tWR
tDH
tDS
tDH
tLD
LTC1599
APPLICATIONS INFORMATION
Description The LTC1599 is a 16-bit multiplying, current output DAC with a 2-byte (8-bit wide) digital interface. The device operates from a single 5V supply and provides both unipolar 0V to - 10V or 0V to 10V and bipolar 10V output ranges from a 10V or -10V reference input. It has three additional precision resistors on chip for bipolar operation. Refer to the Block Diagram regarding the following description. The 16-bit DAC consists of a precision R-2R ladder for the 13LSBs. The 3MSBs are decoded into seven segments of resistor value R (48k typ). Each of these segments and the R-2R ladder carries an equally weighted current of one eighth of full scale. The feedback resistor RFB and 4-quadrant resistor ROFS have a value of R/4. 4-quadrant resistors R1 and R2 have a magnitude of R/4. R1 and R2 together with an external op amp (see Figure 4) inverts the reference input voltage and applies it to the 16-bit DAC input REF, in 4-quadrant operation. The REF pin presents a constant input impedance of R/8 in unipolar mode and R/12 in bipolar mode. The output impedance of the current output pin IOUT1 varies with DAC input code. The IOUT1 capacitance due to the NMOS current steering switches also varies with input code from 70pF to 115pF. IOUT2F and IOUT2S are normally tied to the system analog ground. An added feature of the LTC1599 is a proprietary deglitcher that reduces glitch impulse to 1.5nV-s over the DAC output voltage range. Digital Section The LTC1599 has a byte wide (8-bit), digital input data bus. The device is double-buffered with two 16-bit registers. The double-buffered feature permits the update of several DACs simultaneously. The input register is loaded directly from an 8-bit (or higher) microprocessor bus in a two step sequence. The MLBYTE pin selects whether the 8 input data bits are loaded into the LSB or the MSB byte of the input register. When MLBYTE is brought to a logic low level and WR is given a logic low going pulse, the 8 data bits are loaded into the LSB byte of the input register. Conversely, when MLBYTE is brought to a logic high level and WR is given a logic low going pulse, the 8 data bits are loaded into the MSB byte of the input register. If WR is brought to a logic low level, the existing level of MLBYTE determines which byte is loaded into the input register. If the logic level of MLBYTE is changed while WR remains low, no change will occur. This is because WR is an edge triggered signal and once it goes low it locks out any further changes in MLBYTE. WR must be brought high and then low again to accept the new MLBYTE condition. The second register (DAC register) is updated with the data from the input register when the LD pin is brought to a logic low level. Updating the DAC register updates the DAC output with the new data. The deglitcher is activated on the falling edge of the LD pin. The asynchronous clear pin resets the LTC1599 to zero scale when the CLVL pin is at a logic low level and to midscale when the CLVL pin is at a logic high level. CLR resets both the input and DAC registers. The device also has a power-on reset. Table 1 shows the truth table for the device. Unipolar Mode (2-Quadrant Multiplying, VOUT = 0V to - VREF) The LTC1599 can be used with a single op amp to provide 2-quadrant multiplying operation as shown in Figure 1. With a fixed - 10V reference, the circuit shown gives a precision unipolar 0V to 10V output swing. Bipolar Mode (4-Quadrant Multiplying, VOUT = - VREF to VREF) The LTC1599 contains on chip all the 4-quadrant resistors necessary for bipolar operation. 4-quadrant multiplying operation can be achieved with a minimum of external components, a capacitor and a dual op amp, as shown in Figure 3. With a fixed 10V reference, the circuit shown gives a precision bipolar - 10V to 10V output swing. Op Amp Selection Because of the extremely high accuracy of the 16-bit LTC1599, careful thought should be given to op amp selection in order to achieve the exceptional performance of which the part is capable. Fortunately, the sensitivity of INL and DNL to op amp offset has been greatly reduced compared to previous generations of multiplying DACs. Tables 2 and 3 contain equations for evaluating the effects of op amp parameters on the LTC1599's accuracy when
U
W
U
U
9
LTC1599
APPLICATIONS INFORMATION
configured in unipolar or bipolar modes of operation (Figures 1 and 3). These are the changes the op amp can cause to the INL, DNL, unipolar offset, unipolar gain error, bipolar zero and bipolar gain error. Table 4 contains a partial list of LTC precision op amps recommended for use with the LTC1599. The two sets of easy-to-use design equations simplify the selection of op amps to meet the system's specified error budget. Select the amplifier from Table 4 and insert the specified op amp parameters in either Table 2 or Table 3. Add up all the errors for each category to determine the effect the op amp has on the accuracy of the LTC1599. Arithmetic summation gives an (unlikely) worst-case effect. RMS summation produces a more realistic effect. Op amp offset will contribute mostly to output offset and gain error and has minimal effect on INL and DNL. For the LTC1599, a 500V op amp offset will cause about 0.55LSB INL degradation and 0.15LSB DNL degradation with a 10V full-scale range (20V range in bipolar). For the LTC1599 configured in the unipolar mode, the same 500V op amp offset will cause a 3.3LSB zero-scale error and a 3.45LSB gain error with a 10V full-scale range. While not directly addressed by the simple equations in Tables 2 and 3, temperature effects can be handled just as easily for unipolar and bipolar applications. First, consult an op amp's data sheet to find the worst-case VOS and IB over temperature. Then, plug these numbers in the VOS and IB equations from Table 2 or Table 3 and calculate the temperature induced effects. For applications where fast settling time is important, Application Note 74, entitled "Component and Measurement Advances Ensure 16-Bit DAC Settling Time," offers a thorough discussion of 16-bit DAC settling time and op amp selection.
Table 2. Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in Unipolar Applications
OP AMP VOS (mV) IB (nA) AVOL (V/V) INL (LSB) VOS * 1.2 * (10V/VREF) IB * 0.00055 * (10V/VREF) 10k/AVOL DNL (LSB) VOS * 0.3 * (10V/VREF) IB * 0.00015 * (10V/VREF) 3k/AVOL UNIPOLAR OFFSET (LSB) VOS * 6.6 * (10V/VREF) IB * 0.065 * (10V/VREF) 0 UNIPOLAR GAIN ERROR (LSB) VOS * 6.9 * (10V/VREF) 0 131k/AVOL
Table 3. Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in Bipolar Applications
OP AMP VOS1 (mV) IB1 (nA) AVOL1 VOS2 (mV) IB2 (nA) AVOL2 INL (LSB) VOS1 * 1.2 * (10V/VREF) IB1 * 0.00055 * (10V/VREF) 10k/AVOL 0 0 0 DNL (LSB) VOS1 * 0.3 * (10V/VREF) IB1 * 0.00015 * (10V/VREF) 3k/AVOL1 0 0 0 BIPOLAR ZERO ERROR (LSB) VOS1 * 9.9 * (10V/VREF) IB1 * 0.065 * (10V/VREF) 0 VOS2 * 6.7 * (10V/VREF) IB2 * 0.065 * (10V/VREF) 65k/AVOL2 BIPOLAR GAIN ERROR (LSB) VOS1 * 6.9 * (10V/VREF) 0 196k/AVOL1 VOS2 * 13.2 * (10V/VREF) IB2 * 0.13 * (10V/VREF) 131k/AVOL2
Table 4. Partial List of LTC Precision Amplifiers Recommended for Use with the LTC1599, with Relevant Specifications
Amplifier Specifications VOS V 25 50 60 70 75 IB nA 2 0.35 0.25 20 10 AOL V/mV 800 1000 1500 4000 5000 VOLTAGE NOISE nV/Hz 10 14 14 2.7 5 CURRENT NOISE pA/Hz 0.12 0.008 0.008 0.3 0.6 SLEW RATE V/s 0.25 0.2 0.16 4.5 22 GAIN BANDWIDTH PRODUCT MHz 0.8 0.7 0.75 12.5 90 tSETTLING with LTC1599 s 120 120 115 19 2.5 POWER DISSIPATION mW 46 11 10.5/Op Amp 69/Op Amp 117
AMPLIFIER LT1001 LT1097 LT1112 (Dual) LT1124 (Dual) LT1468
10
U
W
U
U
LTC1599
APPLICATIONS INFORMATION
5V 0.1F VREF 4 R1 8 DATA INPUTS 14 TO 18, 21 TO 23 MLBYTE 13 MLBYTE WR LD CLR WR LD CLR CLVL 12 11 24 CLVL 10 DGND R1 3 RCOM R2 2 R2 1 REF 20 VCC 5 ROFS ROFS RFB 6 RFB 33pF IOUT1 LTC1599 16-BIT DAC 7 2
IOUT2S 19
9
Unipolar Binary Code Table
DIGITAL INPUT BINARY NUMBER IN DAC REGISTER LSB MSB 1111 1111 1111 1111 1000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 ANALOG OUTPUT VOUT -VREF (65,535/65,536) -VREF (32,768/65,536) = -VREF/ 2 -VREF (1/65,536) 0V
Figure 1. Unipolar Operation (2-Quadrant Multiplication) VOUT = 0V to - VREF
5 5V 7 0.1F
1/2 LT1112 VREF 4 R1 8 DATA INPUTS 14 TO 18, 21 TO 23 MLBYTE 13 MLBYTE WR LD CLR WR LD CLR CLVL 12 11 24 CLVL 10 R1 3 RCOM R2
LTC1599
16-BIT DAC IOUT2F IOUT2S DGND 19 9 8 3
Unipolar Binary Code Table
DIGITAL INPUT BINARY NUMBER IN DAC REGISTER LSB MSB 1111 1111 1111 1111 1000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 ANALOG OUTPUT VOUT VREF (65,535/65,536) VREF (32,768/65,536) = VREF/2 VREF (1/65,536) 0V
Figure 2. Noninverting Unipolar Operation (2-Quadrant Multiplication) VOUT = 0V to VREF
+
-
-
6
2
1
20 5 VCC ROFS ROFS RFB
6 RFB 33pF IOUT1 7 2
R2 REF
+
IOUT2F
8
3
-
U
W
+
U
U
LT1001
6
VOUT 0V TO -VREF
1599 F01
1/2 LT1112
1
VOUT 0V TO VREF
1599 F02
11
LTC1599
APPLICATIONS INFORMATION
VREF
4 R1 8 DATA INPUTS 14 TO 18, 21 TO 23 MLBYTE 13 MLBYTE R1
3 RCOM R2
LTC1599
16-BIT DAC IOUT2F IOUT2S DGND 19 9 8 3
WR LD CLR WR LD CLR CLVL 12 11 24
CLVL 10
Bipolar Offset Binary Code Table
DIGITAL INPUT BINARY NUMBER IN DAC REGISTER LSB MSB 1111 1111 1111 1111 1000 0000 0000 0001 1000 0000 0000 0000 0111 1111 1111 1111 0000 0000 0000 0000 ANALOG OUTPUT VOUT VREF (32,767/32,768) VREF (1/32,768) 0V -VREF (1/32,768) -VREF
Figure 3. Bipolar Operation (4-Quadrant Multiplication) VOUT = - VREF to VREF
Precision Voltage Reference Considerations Much in the same way selecting an operational amplifier for use with the LTC1599 is critical to the performance of the system, selecting a precision voltage reference also requires due diligence. As shown in the section describing the basic operation of the LTC1599, the output voltage of the DAC circuit is directly affected by the voltage reference; thus, any voltage reference error will appear as a DAC output voltage error. There are three primary error sources to consider when selecting a precision voltage reference for 16-bit applications: output voltage initial tolerance, output voltage temperature coefficient and output voltage noise. Initial reference output voltage tolerance, if uncorrected, generates a full-scale error term. Choosing a reference with low output voltage initial tolerance, like the LT1236 (0.05%), minimizes the gain error caused by the reference; however, a calibration sequence that corrects for system zero- and full-scale error is always recommended.
A reference's output voltage temperature coefficient affects not only the full-scale error, but can also affect the circuit's INL and DNL performance. If a reference is chosen with a loose output voltage temperature coefficient, then the DAC output voltage along its transfer characteristic will be very dependent on ambient conditions. Minimizing the error due to reference temperature coefficient can be achieved by choosing a precision reference with a low output voltage temperature coefficient and/or tightly controlling the ambient temperature of the circuit to minimize temperature gradients. As precision DAC applications move to 16-bit and higher performance, reference output voltage noise may contribute a dominant share of the system's noise floor. This in turn can degrade system dynamic range and signal-tonoise ratio. Care should be exercised in selecting a voltage reference with as low an output noise voltage as practical for the system resolution desired. Precision voltage references, like the LT1236, produce low output noise in the 0.1Hz to 10Hz region, well below the 16-bit LSB level in 5V
12
+
-
-
6
+
5
1/2 LT1112
7
2
R2 REF
U
1
W
U
U
5V 0.1F
20 5 VCC ROFS ROFS RFB
6 RFB 15pF IOUT1 7 2
1/2 LT1112
1
VOUT -VREF TO VREF
1599 F03
LTC1599
APPLICATIONS INFORMATION
or 10V full-scale systems. However, as the circuit bandwidths increase, filtering the output of the reference may be required to minimize output noise.
Table 5. Partial List of LTC Precision References Recommended for Use with the LTC1599, with Relevant Specifications
REFERENCE LT1019A-5, LT1019A-10 LT1236A-5, LT1236A-10 LT1460A-5, LT1460A-10 INITIAL TOLERANCE 0.05% 0.05% 0.075% TEMPERATURE DRIFT 5ppm 5ppm 10ppm 0.1Hz to 10Hz NOISE 12VP-P 3VP-P 20VP-P
Grounding As with any high resolution converter, clean grounding is important. A low impedance analog ground plane and star grounding should be used. IOUT2F and IOUT2S must be tied to the star ground with as low a resistance as possible. When it is not possible to locate star ground close to IOUT2F and IOUT2S, separate traces should be used to route these pins to star ground. This minimizes the voltage drop from these pins to ground caused by the code dependent current flowing to ground. When the resistance of these circuit board traces becomes greater than 1, the circuit in Figure 4 eliminates voltage drop errors caused by high
2 4 LT1236A-10 5V 6 10V
15V
4 R1 8 DATA INPUTS 14 TO 18, 21 TO 23 MLBYTE 13 MLBYTE R1
3 RCOM R2
2 R2
1 REF
LTC1599
16-BIT DAC
WR LD CLR WR LD CLR CLVL 12 11 24
CLVL 10
DGND 19
IOUT2S 9 6
Figure 4. Driving IOUT2F and IOUT2S with a Force/Sense Amplifier
+
IOUT2F
8
3
-
U
W
U
U
resistance traces. This preserves the excellent accuracy (1LSB INL and DNL) of the LTC1599. A 16-Bit, 4mA to 20mA Current Loop Controller for Industrial Applications Modern process control systems must often deal with legacy 4mA to 20mA analog current loops as a means of interfacing with actuators and valves located at a distance. The circuit in Figure 5 provides an output to a current loop controlled by an LTC1599, a 16-bit current output DAC. A dual rail-to-rail op amp (U1, LT1366) controls a P-channel power FET (Q2) to produce a current mirror with a precise 8:1 ratio as defined by a resistor array. The input current to this mirror circuit is produced by a grounded base cascode stage using a high gain transistor (Q1). The use of a bipolar transistor in this location results in an error term associated with U1B and Q1's base current (- 0.2% for the device shown). For control applications however, absolute accuracy of the output to an actuator is usually not required. If a higher degree of absolute accuracy is required, Q1 can be replaced with an N-channel JFET; however, this requires a single amplifier at U1B with the ability to drive the gate below ground. An enhancement mode N-channel FET can be used in place of Q1 but MOSFET leakage current must be considered and gate overdrive must be avoided.
0.1F
20 VCC
5 ROFS ROFS RFB
6 RFB 33pF IOUT1 7 2
LT1001
6
VOUT 0V TO -10V
+
LT1001
3
-
2
1599 F04
13
LTC1599
APPLICATIONS INFORMATION
The output current of the DAC is converted to a voltage via U3 (LT1112), producing 0V to - 2.5V at Pin 1 of U3. The resulting current in Q1 is determined by two elements of resistor array, RN1 (3mA max). The emitter of Q1 is maintained at 0V by the action of U1B. In applications that do not require 16-bit resolution and accuracy, the LTC1599 can be replaced by the 14-bit parallel LTC1591. Furthermore, the resistor array can be substituted with discrete resistors, and Q2 could be replaced by a high gain bipolar PNP; for example, an FZT600 from Zetex. No trim is provided a shown, as it is expected that software control is preferable. The output range of 4mA to 20mA is defined by software, as the full output range is nominally 0mA to 24mA. U1 is a rail-to-rail amplifier that can operate on suppy voltages up to 36V. This defines the maximum voltage on the loop power. If higher loop voltages are required, a separate low power amplifier at U1A, powered by a zener regulated supply and referenced to loop power, would allow voltages up to the breakdown voltages of Q1 and Q2. In the example shown, the use of a dual op amp requires a zener clamp to protect the gate of the MOS power transistor. If a separate shunt-regulated supply is provided for the amplifier replacing U1A, the gate clamp (Z1) is not required. As shown, this topology uses the LTC1599's internal divider (R1 and R2) to reduce the reference from 5V to 2.5V. If a 2.5V reference is used, it can be connected directly to REF (Pin 1). Alternatively, if the op amp is powered such that it has -10V output capability, the divider and amplifier prior to the REF input are not required and ROFS can be used for other purposes such as offset trim. The two RN1 resistors at the emitter of Q1 must be changed in this case. Note that the output of the current transmitter shows a network that is intended to provide a first line of defense against ESD and prevent oscillation (1000pF and 10) that could otherwise occur in the power MOSFET if lead inductance were more than a few inches. C1 should be as close as possible to Q2. Using MOSFETs that have higher threshold voltages may require changing Z1 in order to allow full current output.
LOOP POWER 0.1F 2 12 LT1460-5 4 6 0.1F 6 IF 2.5V REF USED CONNECT DIRECTLY TO REF 5 RN1 15 10 RN1 7 5V 0.1F 7 3 2 C2 8 100pF 1 R3 1k Z1 R4 6.2V 1k 3 14 4 13 5 12 6 11 RN1
24V
+
1/2 LT1112
U1A 1/2 LT1366
-
4 R1 8 DATA INPUTS 14 TO 18, 21 TO 23 MLBYTE 13 MLBYTE R1
3 RCOM R2
2 R2
1 20 REF VCC
5 ROFS ROFS RFB
6 RFB C3 33pF 6
U1B 1/2 LT1366
IOUT2S DGND CLVL 10 24 19
9 RN1 = 400 x 8 RESISTOR ARRAY
WR LD CLR WR LD CLR CLVL 12 11
Figure 5. 16-Bit Current Loop Controller for Industrial Applications
14
+
U2 LTC1599
16-BIT DAC IOUT2F 8 3
-
IOUT1
7
2
U3 1/2 LT1112
1
1
RN1
16 9
+
-
+
-
U
W
U
U
Q2 Si9407AEX
R5 10 IOUT C1 1000pF
4
5
7 R6 1k
Q1 MMBT6429 HFE = 500
RN1
8
LTC1599
APPLICATIONS INFORMATION
A 16-Bit General Purpose Analog Output Circuit Industrial applications often use analog signals of 0V to 5V, 0V to 10V, 5V or 10V. The topology in Figure 6 uses an LTC1599 to produce a universal analog output, capable of operation over all these ranges, with only software configuration. High precision analog switches are used to provide uncompromising stability in all ranges and matched resistors internal to the LTC1599 are used, as well as a configuration that minimizes the effects of channel resistance in the switches. Note that in all cases the analog switches have minimal current flowing through them. The use of unbuffered analog switches in series with the feedback/divider resistors would result in an error because of temperature coefficient mismatch between the internal DAC resistors and the switch channel resistances, as well as the channel resistance variation over the signal range. Quad analog switch U3 (DG212B) allows configuration of feedback terms and selection of the reference voltage. Switch C allows the buffered reference voltage to be injected into the summing node via Pin 5 (ROFS) for bipolar outputs. When active, switch D places ROFS in parallel with RFB, producing an output at full scale voltage equal to the voltage at the REF pin of the LTC1599. The other switches in U3 (A and B) are used to select the 10V reference produced by the LT1019, or 5V produced by the R3 and R4 divider. An inexpensive precision divider can be implemented using an 8-element resistor array, paralleling four resistors for R3 and four resistors for R4. Symmetry in the interconnection of these resistors will ensure compensation for temperature gradient across the resistor array. An alternative to a resistor divider is the LTC1043 switched capacitor building block. It can be configured as a high precision divide-by-2. Please consult the LTC1043 data sheet for more information. The NOR gate (U4) ensures that switches C and D are not enabled simultaneously. This eliminates contention between the reference buffer and the output amplifier. This topology can be modified to accept a high current buffer following the LT1112, if higher output current levels are required or difficult loads need be driven. Adjustment of CFB's value may be required for the buffer amplifier chosen. Note that the analog switches must handle the full output swing in this configuration, but there is a variety of suitable switches on the market including the LTC201. The DG212B as shown is a newer generation part with lower leakage, providing a performance advantage. The DG333A, a quad single-pole, double-throw switch, could be used for a 2-channel version similar to this circuit. Alternatively, a single channel can be created with the additional switches used as switched capacitor divideby-2, as shown on the LTC1043 data sheet. In choosing analog switches, keep in mind the logic levels and the signal levels required.
Table 1. Configuration Settings for the Various Output Ranges
VOUT MODE 0V to 5V 0V to 10V - 5V to 5V -10V to 10V REFSEL 1 1 1 0 BIPOLAR/UNIPOLAR 0 0 1 1 GAIN 0 1 1 1
U
W
U
U
15
LTC1599
9 U3C 11 16 1 U4 2 3
BIPOLAR/UNIPOLAR GAIN
2 16 5
U3A 1
APPLICATIONS INFORMATION
U5 LT1019-10 8 6 7 4 R1 RCOM RFB RFB R1 R2 ROFS 3 21 20 R2 REF VCC 5 ROFS 6 U1B 1/4 LT1114 7 0.1F
4
0.1F
R3 5k
6
-
R4 5k
U3B
CFA 15V 33pF
8 DATA INPUTS 14 TO 18, 21 TO 23 MLBYTE WR LD CLR CLVL 10 WR LD CLR CLVL 12 11 24 13 MLBYTE U2 LTC1599 16-BIT DAC
R1 = R2 = 5k U3A TO U3D = 1/4 DG212B U4A, U4B = 1/4 HC02 LT1019 PINOUT FOR SO-8 PACKAGE LT1114 PINOUT FOR SO PACKAGE
IOUT2S DGND 19
9
Figure 6. 16-Bit General Purpose Analog Output Circuit
+
IOUT2F
8
3
-
IOUT1
7
2
8 U1A 1/4 LT1114 4
0.1F 1
VOUT
0.1F
-15V
OPTIONAL HIGH CURRENT BUFFER LT1010 LT1206 LT1210
1599 F06
U
+
6 10V 3 14
2
-
15V 15 U1D 1/4 LT1114 10 U1C 1/4 LT1114 5V
+ -
11 R3 100k
12
15 U3D
14
+
W
REFSEL
5 6
U4
4
U
10
U
16
LTC1599
APPLICATIONS INFORMATION
Interfacing to the 68HC11 The circuit in Figure 7 is an example of using the 68HC11 to control the LTC1599. Data is sent to the DAC using two 8-bit parallel transfers from the controller's Port B. The WR signal is generated by manipulating the logic output on Port A's bit 3, the MLBYTE command is sent to the DAC using Port A's bit 4, and the LD command comes from the SS output on Port D's bit 5. The sample listing 68HC11 assembly code in Listing A is designed to emulate the Timing Diagram found earlier in this data sheet. After variable declaration, the main portion of the program retrieves the least significant byte from memory, forces MLBYTE and WR to a logic low, and then writes the low byte data to Port B. It then sets WR and
8-BIT PARALLEL PORT B 68HC11 PORT A, BIT 3 PORT D, BIT 5 PORT A , BIT 4 LTC1599 WR LD MLBYTE
************************************************************ * * * This example program uses 8-bit parallel port B, port A and port D * * to transfer 16-bit parallel data to the LTC1599 16-bit current output * * DAC. Port B at $1004 is used for two eight bit transfers. Port A, * * bit 3 is used for the LTC1599's WR command and bit 4 is used for the * * MLBYTE command. Port D' SS output is used for the LTC1599's LD * * command * * * ************************************************************ * ***************************************** * 68HC11 register definitions * ***************************************** * * PIOC EQU $1002 Parallel I/O control register * "STAF,STAI,CWOM,HNDS, OIN, PLS, EGA,INVB" PORTA EQU $1000 Port A data register * "Bit7,Bit6,Bit5,Bit4,Bit3,Bit2,Bit1,Bit0" PORTB EQU $1004 Port B data register * "Bit7,Bit6,Bit5,Bit4,Bit3,Bit2,Bit1,Bit0" PORTD EQU $1008 Port D data register * " - , - , SS* ,CSK ;MOSI,MISO,TxD ,RxD " DDRD EQU $1009 Port D data direction register SPCR EQU $1028 SPI control register MBYTE EQU $00 This memory location holds the LTC1599's bits 15 - 08 LBYTE EQU $01 This memory location holds the LTC1599's bits 07 - 00 * ***************************************** * Start OUTDATA Routine * ***************************************** * ORG $C000 Program start location INIT1 LDAA #$2F -,-,1,0;1,1,1,1 * -, -, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X STAA PORTD Keeps SS* a logic high when DDRD, Bit5 is set LDAA #$38 -,-,1,1;1,0,0,0 STAA DDRD SS* , SCK, MOSI are configured as Outputs * MISO, TxD, RxD are configured as Inputs * DDRD's Bit5 is a 1 so that port D's SS* pin is a general output
U
W
U
U
1599 F07
Figure 7. Using the 68HC11 to Control the LTC1599
MLBYTE high. Next, the most significant byte is copied from memory and WR is again asserted low. The high byte is written to Port B and WR is returned high. The transfer of the 16 bits is completed by cycling the LD input low and then high using the SS output on Port D.
17
LTC1599
APPLICATIONS INFORMATION
GETDATA PSHX PSHY PSHA LDY #$1000 Setup index * ***************************************** * Retrieve DAC data from memory and * * send it to the LTC1599 * ***************************************** * LDAA LBYTE Retrieve the least significant byte from memory BCLR PORTA,Y %00010000 This sets PORTA, Bit4 output to a logic * low, forcing MLBYTE input to a logic low BCLR PORTA,Y %00001000 This forces a low on the LTC1599's WR pin STAA PORTB Transfer the least significant byte to the DAC BSET PORTA,Y %00001000 This forces a high on the LTC1599's WR pin BSET PORTA,Y %00010000 This sets PORTA, Bit4 output to a logic * high, forcing MLBYTE to a logic high LDAA MBYTE Retrieve the most significant byte from memory BCLR PORTA,Y %00001000 This forces a low on the LTC1599's WR pin STAA PORTB Transfer the most significant byte to the DAC BSET PORTA,Y %00001000 This forces a high on the LTC1599's WR pin * ******************************************* * The next two instructions exercise * * the LD input, latching the data * * that was just loaded * ******************************************* * BCLR PORTD,Y %00100000 LD goes low BSET PORTD,Y %00100000 and returns high * ******************************************* * Data transfer routine completed * ******************************************* * PULA Restore the A register PULY Restore the Y register PULX Restore the X register RTS
18
U
W
U
U
LTC1599
TYPICAL APPLICATION
16-Bit VOUT DAC Programmable Unipolar/Bipolar Configuration
UNIPOLAR/ BIPOLAR
LT1236A-10
4 R1 R1 8 DATA INPUTS 14 TO 18, 21 TO 23
3 RCOM R2
LTC1599
16-BIT DAC
IOUT2S WR LD CLR CLVL DGND 19
9
1596 TA02
WR LD CLR CLVL
12 11
24
10
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted. G Package 24-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
8.07 - 8.33* (0.318 - 0.328) 24 23 22 21 20 19 18 17 16 15 14 13
5.20 - 5.38** (0.205 - 0.212)
1.73 - 1.99 (0.068 - 0.078)
0 - 8 7.65 - 7.90 (0.301 - 0.311) 0.05 - 0.21 (0.002 - 0.008)
0.13 - 0.22 (0.005 - 0.009)
0.55 - 0.95 (0.022 - 0.037)
0.25 - 0.38 (0.010 - 0.015) NOTE: DIMENSIONS ARE IN MILLIMETERS *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.152mm (0.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE
0.65 (0.0256) BSC
1 2 3 4 5 6 7 8 9 10 11 12
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
+
IOUT2F
8
3
-
-
2
+
4
6
3
LT1001
6
2 1 R2 REF
-
15V
2
2
+
U
U
16
15
14
LTC203AC
1
2 3
3
LT1468
6
5V 0.1F
20 VCC
5 ROFS ROFS RFB
6 RFB 15pF IOUT1 7 2
LT1468
6
VOUT
G24 SSOP 1098
19
LTC1599
TYPICAL APPLICATION
17-Bit Sign Magnitude DAC with Bipolar Zero Error of 140V (0.92LSB at 17 Bits) at 25C
16 15 14
15V
2 1 6 4 SIGN BIT R1 R1 8 DATA INPUTS 14 TO 18, 21 TO 23 3 RCOM 2 3
LT1236A-10 4
R2
LTC1599
16-BIT DAC
IOUT2S WR LD CLR CLVL DGND 19
9
1596 TA03
WR LD CLR CLVL
12 11
24
10
PACKAGE DESCRIPTION
0.300 - 0.325 (7.620 - 8.255) 0.130 0.005 (3.302 0.127) 0.020 (0.508) MIN 0.045 - 0.065 (1.143 - 1.651)
Dimensions in inches (millimeters) unless otherwise noted. N Package 24-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
1.265* (32.131) MAX
24 23 22 21 20 19 18 17 16 15 14 13
0.009 - 0.015 (0.229 - 0.381)
(
+0.035 0.325 -0.015 +0.889 8.255 -0.381
)
0.125 (3.175) MIN
0.065 0.255 0.015* (1.651) (6.477 0.381) TYP 0.100 (2.54) BSC 0.018 0.003 (0.457 0.076)
1 2 3 4 5 6 7 8 9 10 11 12
N24 1098
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
RELATED PARTS
PART NUMBER LT1236 LT1468 LTC1591/LTC1597 LTC1595/LTC1596 LTC1650 LTC1657 LTC1658 DESCRIPTION Precision Reference 16-Bit Accurate Op Amp Parallel 14/16-Bit Current Output DACs Serial 16-Bit Current Output DACs 16-Bit Voltage Output DAC 16-Bit Parallel Voltage Output DAC 14-Bit Rail-to-Rail Micropower DAC COMMENTS 0.05% Initial Accuracy, 5ppm Temperature Drift 90MHz Gain Bandwidth, 22V/s Slew Rate On-Chip 4-Quadrant Resistors Low Glitch, 1LSB Maximum INL, DNL Low Power, Deglitched, 4-Quadrant Multiplying VOUT DAC, 4.5V Output Swing Low Power, 16-Bit Monotonic Over Temperature, Multiplying Capability Low Power Multiplying VOUT DAC in MSOP. Output Swings from GND to REF.
1599f LT/TP 1199 4K * PRINTED IN USA
20
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
(c) LINEAR TECHNOLOGY CORPORATION 1999
+
IOUT2F
8
3
-
-
2
+
U
U
LTC203AC
3
5V LT1468 6 0.1F
15pF 2 R2 1 REF 20 5 VCC ROFS ROFS RFB IOUT1 7 2 6 6 RFB 20pF
LT1468
VOUT

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